In general, a semiconductor memory device includes a plurality of memory cells for storing data and requires a data output controller that outputs data to an external chip cell by reading the data stored in the memory cell.
FIG. 1 is a circuit view of a conventional data output controller.
As shown in FIG. 1, when a read signal (readS) is activated, the conventional data output controller outputs a clock enable signal clkenb having a predetermined activation period in synchronization with a signal Node B output from a delay terminal. Such an enable signal is used for generating a data clock.
In the conventional data output controller, it is important to ensure a margin between the read signal and the signal Node B having a predetermined pulse width. If the read signal has a sufficient pulse width, the data output controller can be normally operated.
However, if the read signal has a narrow pulse width, as shown in FIG. 2, there is no period where both signal Node B and read signal are high levels, so that the clock enable signal clkenb may not be maintained at a low level. As a result, if the read signal has a narrow pulse width, data clocks rclk and fclk are not generated, so that a DRAM may not normally output data.